1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundancy circuit to reduce the chip area and to improve the redundancy efficiency.
2. Description of the Related Art
As the goals of achieving higher integration and larger capacity for semiconductor memory devices are reached, the size of a memory chip becomes increasingly larger. This increase in the size of the memory chip results in a lower wafer yield. Redundancy technology to repair defective memory cells has been used in semiconductor memory devices as one of the ways to increase the wafer yield. Redundancy technology provides a semiconductor memory device with redundant memory cells so that defective memory cells are replaced with corresponding, non-defective, redundant memory cells.
FIG. 1 illustrates a memory array block of a general semiconductor memory device. The semiconductor memory device 10 includes a plurality of sectors 100 and 200. The sectors 100 and 200 each include a plurality of memory blocks 110, 120, 130, 210, 220 and 230 each having a plurality of memory cells, a global column decoder 102 and 202, a sense amplifier 104 and 204, and a write driver 106 and 206. Each of the memory blocks 110, 120, 130, 210, 220 and 230 includes a row decoder 112, 122, 132, 212, 222 and 232 for driving word lines of the memory cells, and a column decoder 114, 124, 134, 214, 224 and 234 for selecting bit lines BL0, BL1, . . . , BLk of the memory cells. The bit lines selected from each of the memory blocks 110, 120, 130, 210, 220 and 230 are connected to global bit lines GBL00, GBL01, . . . , GBLJ0, GBLJ1. A global column decoder 102 selects one of the global bit lines GBL00, GBL01, . . . , GBLJ0, GBLJ1, . . . and connects the selected global bit line to the sense amplifier 104 and 204 and the write driver 106 and 206. Each of the memory blocks 110, 120, 130, 210, 220 and 230 has a corresponding redundancy memory block 116, 126, 136, 216, 226 and 236, respectively, consisting of a plurality of redundant memory cells. The redundancy memory cells are substituted for the defective cells in the memory blocks. In addition to the defective cells, the substitution of the redundant memory cells for the defective cells is also applicable to defective bit lines in case that the bit lines BL0, BL1, of the memory blocks 110, 120, 130, 210, 220 and 230 are shorted or opened.
Addresses of the defective cells and the defective bit lines are stored in a fuse box of the memory device 10. If addresses are inputted to select the defective cells or the defective bit lines, the row decoder 112, 122, 132, 212, 222 and 232 and the column decoder 114, 124, 134, 214, 224 and 234 are cut and corresponding redundant memory cells are selected according to the addresses programmed in the fuse box. The fuse box has as many fuses as the number of the addresses for addressing the memory cells of the memory blocks 110, 120, 130, 210, 220 and 230.
The semiconductor memory device 10 can be defective not only if the memory cells or the bit lines BL are defective but also if the global bit lines GBL00, GBL01, . . . , GBLJ0, GBLJ1, . . . are shorted or opened. If the above-described conventional method for repairing the defective cells or the defective bit lines is used to repair the defective global bit lines, the fuse box should include the fuses corresponding to the addresses required to address the sectors 100 and 200. Therefore, the semiconductor memory device requires a redundancy circuit that has fuses corresponding to each of the memory block addresses and the sector addresses, that is, memory block address fuses and sector address fuses. Accordingly, the redundancy circuit occupies a larger area.
However, in the case where only the defective memory cells or the defective bit lines should be repaired, the sector address fuses of the redundancy circuit are not used. This implies that the redundancy efficiency is low with respect to the area of the redundancy circuit. Additionally, the redundancy circuit occupies a larger area than necessary.